1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device provided with a DMOS (Double-Diffused Metal Oxide Semiconductor) and a bipolar transistor as well as a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device employing a bipolar transistor in an output circuit has been known. For example, Japanese Patent Laying-Open No. 5-3293 has disclosed a semiconductor integrated circuit for providing an output-stage inverter circuit formed of a combination of a vertical PNP transistor and a DMOSFET.
As related arts, Japanese Patent Laying-Open No. 8-227945 has disclosed a method of forming an integrated circuit based on a BiCDMOS process, and Japanese Patent Laying-Open No. 2002-198448 has disclosed a method of manufacturing a semiconductor device by a BiCMOS process.
In the semiconductor integrated circuit disclosed in the foregoing Japanese Patent Laying-Open No. 5-3293, first and second epitaxial layers are formed on a semiconductor substrate, and an n+-type collector resistance region, a p-type base region and an n+-emitter region of an npn transistor are formed in the second epitaxial layer. The DMOSFET is also formed on the second epitaxial layer.
In the semiconductor integrated circuit disclosed in the foregoing Japanese Patent Laying-Open No. 5-3293, it is necessary to lower a concentration in the second epitaxial layer for lowering a saturation voltage of the DMOSFET. However, the low concentration in the second epitaxial layer impairs a breakdown voltage between a collector and a base of the npn transistor.